The present invention generally relates to integrated circuits, and, more particularly, to power-on-reset circuits.
Many integrated circuits (ICs) including system-on-chip (SoC) integrate various digital and analog components on a single chip. The components may include sequential elements such as flip-flops and combinational elements such as multiplexers and encoders. Such ICs are connected to external voltage sources for receiving supply voltages and the digital and analog components operate at a supply voltage level generated by the external voltage source. The IC is powered down by switching off the external voltage source, and when powered back on, the device is reset.
The IC is powered on by switching on the external voltage source. The supply voltage level received by the IC gradually ramps-up to the operating voltage level. However, during ramp-up, the supply voltage level is less than the operating voltage level for a short time, at which time the digital and analog components of the IC may malfunction and possibly damage the IC or set the IC in an indeterminate state. A power-on-reset (POR) circuit is provided to prevent these conditions.
The POR circuit receives the supply voltage from the external voltage source and generates a reset signal when the supply voltage level exceeds a threshold value. During power-up, when the supply voltage level is less than the threshold value, the POR circuit generates a logic low reset signal, which is provided to the digital and analog components and which places the digital and analog components in a known state (i.e., a reset state). Thus, the POR circuit sets the IC in a reset mode and ensures proper operation of the IC during power-up. When the supply voltage exceeds the threshold value, the POR circuit sets the reset signal high, de-asserting the reset state, which causes the IC to exit the reset state and begin operating. The threshold voltage level at which the POR circuit de-asserts the reset state is also referred to as a POR de-assertion threshold.
During the IC design stage, the POR de-assertion threshold is set at an optimum voltage level. If the POR de-assertion threshold exceeds the optimum voltage level, the IC remains in the reset mode, which delays the IC from being ready to function after power-up. Thus, the performance of the IC is negatively impacted. If the POR de-assertion threshold is less than the optimum voltage level, the digital and analog components may not be properly reset and thus may cause functional errors. Thus, it is essential that the POR de-assertion threshold be substantially equal to the optimum voltage level.
However, the POR de-assertion threshold can be affected by various factors such as process variations during fabrication, including within-die variations, lot-to-lot variations, die-to-die variations, wafer-to-wafer variations, etc. The POR circuit may also be sensitive to temperature, layout, and/or process parameters. Thus, to ensure high performance of the fabricated IC, it is essential to determine the POR de-assertion threshold during the testing and qualification stages.
Generally, a test IC is used to measure the POR de-assertion threshold. The POR circuit of the test IC is connected to an analog test pad and an external voltage source is used to provide a supply voltage to the test IC. The POR circuit provides the reset signal as an input to the analog test pad. As the supply voltage ramps-up, a transition voltage level of the supply voltage at which the reset signal transitions from low to high is measured. The transition voltage level is indicative of the POR de-assertion threshold of the POR circuit. This method of testing the POR circuit requires the addition of a dedicated analog test pad, which is undesirable due to the increased cost of adding the analog test pad.
Another technique of testing a POR circuit of a test IC includes connecting the output of the POR circuit to a test flip-flop. Before power-up, the test flip-flop is set to a known state. Then, as the supply voltage ramps-up, the output of the test flip-flop changes state at a transition voltage level of the supply voltage where the reset signal transitions from low to high. A processor core of the test IC polls the test flip-flop output to detect a change in its output. The processor core also monitors the supply voltage. Based on the transition, the processor core measures the POR de-assertion threshold of the POR circuit. However, the supply voltage required for the processor core to operate and poll the output of the test flip-flop exceeds the optimum voltage level of the POR circuit, so by the time the processor core can monitor the flip-flop, the POR de-assertion threshold has already been exceeded, so this method is not accurate.
A technique to overcome the aforementioned problems is to include a first set of input/output (IO) pads, a duplicate POR circuit and a driver circuit in the IC. The driver circuit is connected to the output of the duplicate POR circuit and to a test IO pad of the first set of IO pads. The driver circuit and the duplicate POR circuit receive a supply voltage. As the supply voltage ramps-up and exceeds the POR de-assertion threshold, the output of the duplicate POR circuit transitions from low to high. The driver circuit detects this transition at the output of the POR circuit and changes an impedance state of the test IO pad. A tester connected to the test IO pad detects the change in the impedance, and thereby determines the POR de-assertion threshold of the duplicate POR circuit. However, this method requires the first set of IO pads and the driver circuit, which increase the area overhead and power consumption of the IC.
It would be advantageous to have an IC with a testable power-on-reset (POR) circuit that prevents the IC from being set in an indeterminate state.